High-speed, high resolution and radiation-hardened analog to digital data converter
A Spanish SME has developed a novel radiation-hardened A/D (analog to digital) converter that presents a sampling rate of 100 Msps (Megasamples per second), 12-bit resolution and an effective resolution (ENOB, “effective number of bits”) of 10.4 bits for the aircraft and space industries, as well as for automotive and scientific-medical applications. The SME is interested in getting in contact with electronic devices manufacturers for commercial agreements with technical assistance.
The developer is looking for Electronics system integrators who are interested in using this data converter technology to be included in those systems that they develop. The Spanish SME will provide this technology to the potential partner as well as technical support for a right exploitation according to their needs.
A Spanish SME has developed a novel radiation-hardened A/D converter that presents a sampling rate of 100 Msps (Megasamples per second), 12-bit resolution and an effective resolution (ENOB, “effective number of bits”) of 10.4 bits. The device is a European analog-to-digital converter (ADC) with 10.4 effective bit resolution for 2Vpp input signal at a maximum sampling frequency of 100Msps. Its application targets high-reliability uses under radiation environments in defense, aeronautic, industry and medical instrument fields. The ADC product comprises a dedicated Sample & Hold Amplifier (SHA) and a multi-stage Pipeline ADC with digital correction and robust design for a high-reliability operation in critical applications where the environment variable (high range temperature variations). The Analog-to-Digital Converter (ADC) is integrated in a CMOS technology (“Complementary Metal-Oxide Semiconductor”), which means that these circuits can be integrated with standard digital circuits on the same substrate, within the same integrated circuit. This fact allows the converter to provide functionalities such as: * Ability to reconfigure the system. * Processing. * Control flows. Main features of the technology are: Resolution: 12 bits SNDR (noise and distortion ratio): 64,4dB Sampling frequency: 100MHz Input voltage: 2Vpp Input bandwidth:>75MHz Low power: 300mW @100MHz Radiation hardness: TID: 300 kRad (Si) SEFI (Sequential Electronic Fuel Injection): Failure immune up to 80 MeV·cm2/mg SEL (Single-Event Latchup): Failure immune up to 80 MeV·cm2/mg High-reliability CQFP-48 pins Temperature range: -55ºC / 125ºC Functionality: Digital correction Serial port interface (SPI) Low-jitter differential clock receiver. Duty-Cycle Stabilization (DCS) Analog gain: x2, x4 Adaptation of the consumption according to the conversion speed The Spanish SME is interested in getting in contact with Electronics manufacturets for commercial agreements with technical assistance. They would embed this technology into their products to give more added value
Advantages and innovations
By this innovation of incorporating these functionalities in the same chip, the mixed signal system achieves the following competitive advantages: a) Multiple operating modes: the same system can be used in the implementation of different types of applications. b) Increase in the level of system integration, since functionalities that are implemented in devices, external to the mixed signal integrated circuits, such as FPGAs or microprocessors, can be incorporated into the same integrated circuit that contains the mixed signal circuit. This means a reduction in the number of components to be used in the implementation of the application. This leads to reduced system dimensions, reduced cost and increased reliability. For example, the probability of error decreases on-board systems by reducing the number of built-in components. Reduction of the energy consumption of mixed signal circuits and the high-level systems that incorporate it. The power consumption at the maximum sampling rate is 300mW. c) The converter consists of a complex mixed-signal “System-on-Chip” (SoC), which contains the circuitry for generating voltages and reference currents, the programming logic and digital post processing (correction and output format generation) and the core of the pipeline converter itself, coexisting on a single monolithic integration. Thus, it avoids the need for dedicated external pads, achieving a size and complexity reduction of both the encapsulation and the PCB (Printed Circuit Board) level system, and thus reducing the probability of failure.
Under development/lab tested
Intellectual Property Rights (IPR)
Granted patent or patent application essential
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